5th Workshop on Heterogeneous Composable and Disaggregated Systems

Co-located with ASPLOS 2026

Pittsburgh, USA

March 23, 2026

Workshop Overview

Abstract

The future of computing systems is inevitably embracing a disaggregated and composable pattern: from clusters of computers to pools of resources that can be dynamically combined together and tailored around application requirements. With new interconnects for interfacing CPU, memory and peripherals becoming a commodity (e.g., CXL), disaggregation and composability in computer systems is expected to become a predominant design pattern. This paradigm change increases the level of heterogeneity from what is possible with statically defined servers to software-defined dynamically composed servers, resulting in an increased memory and accelerators capacity/availability and improved resource utilization in a cost-effective way, reducing the overall total cost of ownership. This new class of systems, that we term Heterogeneous and Composable Disaggregated Systems (HCDS), provide a system design approach for reducing the imbalance between workloads resource requirements and the static availability of resources in a computing system, while making room for novel distributed system approaches in processes communication and data exchange.
The HCDS workshop aims at exploring the novel research ideas around composable disaggregated systems and their integration with operating systems and software runtimes to maximize the benefit perceived from user workloads.

Important Dates

These dates are tentative and may still change.

  • Paper submission deadline: January 23, 2026 January 30, 2026 (AoE)
  • Author notification: February 13, 2026 February 20, 2026
  • Camera ready submissions: February 20, 2026 February 27, 2026
  • Workshop: March 23, 2026

Submission Link

Submit your work here

Call for Papers

Heterogeneous and Composable Disaggregated Systems (HCDS), provide a system design approach for reducing the imbalance between workloads resource requirements and the static availability of resources in a computing system, while making room for novel distributed system approaches in processes communication and data exchange.
The HCDS workshop aims at exploring the novel research ideas around composable disaggregated systems and their integration with operating systems and software runtimes to maximize the benefit perceived from user workloads.

Papers are solicited from the areas, including, but not limited to:

Hardware and Prototyping

  • Novel composable systems architectures (e.g., CXL based)
  • Composable system prototypes and proof-of-concept
  • Interconnect technologies (such as CXL)
  • Memory pooling, and memory disaggregation

Modeling and Evaluation

  • Heterogeneous Composable Systems simulation
  • Characterization of heterogeneous composable systems from the perspective of performance, energy consumption and reliability
  • New algorithms and performance models to manage and use HCDS
  • Memory pooling, and memory disaggregation

System software and programming models/tools

  • Operating system designs to support HCDS, such as memory profiling methods, memory management (e,g, page migration and allocation)
  • Control plane software and runtime systems for management of composable systems
  • Programming models for heterogeneous composable memory
  • Analysis / profiling tools and techniques for composable systems
  • Virtualization for composable heterogeneous systems

Applications and Use cases

  • Use cases for heterogeneous composable systems, such as (but not limited to) deep-learning and large language model (llm) inference/serving/training/fine-tuning, agentic AI systems, data-intensive analytics, data input pipelines/streaming and scientific and HPC applications
  • AI system decomposition (e.g., distributed inference in Dynamo) for system disaggregation
  • CXL memory sharing and pooling for AI
  • Co-design of AI model and system disaggregation

Submission Instructions

Each manuscript will be evaluated with a double-blind review process. Authors must omit at submission time their names or any information that can disclose their identity. Manuscripts length must be 4-6 pages including figures and tables but excluding references. All manuscripts must use the sigplan ACM conference style. It is also expected that all accepted papers will be presented at the workshop by one of the authors. Papers accepted to the workshop will have the chance to be published on the ACM Digital Library following the new ACM open access publishing model.

We offer the possibility to opt-out from publishing submitted work to the ACM proceedings. This applies for instance to authors wishing to re-submit an extended version to another venue that does not allow the work to have appeared in official proceedings or, the authors are not part of the ACM open network and do not have the funds for supporting the proceedings processing costs. In such case, if your manuscript is accepted, it will only be published on the workshop website. If you are wishing to do so, send the organizers an email right after submitting your manuscript.

Important note to authors about the new ACM open access publishing model
 ACM has introduced a new open access publishing model for the International Conference Proceedings Series (ICPS). Authors based at institutions that are not yet part of the ACM Open program and do not qualify for a waiver will be required to pay an article processing charge (APC) to publish their ICPS article in the ACM Digital Library. To determine whether or not an APC will be applicable to your article, please follow the detailed guidance here.
Further information may be found on the ACM website, as follows:

Please direct all questions about the new ACM publishing model to icps-info@acm.org

Keynote

Decentralizing the Brain: From CPU-Centric Servers to Intelligent Composable Resources

Alexandros (Alex) Daglis (University of Edinburgh and Georgia Tech)

Abstract: Modern computing is undergoing a dual transformation: software is decomposing into fine-grained microservices, while hardware is disaggregating into composable resource pools. While these trends maximize elasticity and consolidation, they have reached a critical inflection point where the network is now the primary determinant of performance. Despite rapid advancements in interconnect bandwidth and latency, our legacy hardware interfaces introduce significant efficiency bottlenecks.

In this keynote, we will explore why the future of disaggregated systems requires a departure from the CPU-centric monoculture. I will first argue for raising the hardware interface from simple byte-delivery and load/store operations to higher-level RPC-aware semantics and richer memory operations. By making the network and memory systems more "workload-aware," system primitives crucial for performance—such as task orchestration and load balancing—can be automated with microsecond-scale precision. Second, I will discuss the "Disaggregation Paradox": as we push compute and memory resources further away to achieve composability, we must introduce intelligence closer to the data to survive the latency wall. Drawing on relevant examples from a decade of research, this talk presents a vision for how addressing these shifting architectural boundaries charts a scalable path for the next generation of high-performance, highly efficient composable architectures.

Committees

Organizing Committee

  • Christian Pinto (IBM Research Europe, Ireland)
  • Dong Li (UC Merced, CA, USA)
  • Thaleia Dimitra Doudali (IMDEA Software Institute, Spain)
  • Christina Giannoula (University of Toronto, Canada)
  • Jie Ren (William & Mary, VA, USA)
  • Dimosthenis Masouros (National Technical University of Athens, Greece)

Program Co-Chairs

  • Christina Giannoula (Max Planck Institute for Software Systems)
  • Dimosthenis Masouros (National Technical University of Athens, Greece)

Program Committee

  • Alexandros Daglis (Georgia Institute of Technology)
  • Alireza Khadem (University of Michigan)
  • Anatole Lefort (Technical University of Munich)
  • Andreas Grapentin (IBM Germany Research & Development)
  • Archit Patke (University of Illinois Urbana-Champaign)
  • Asif Ali Khan (Technical University of Dresden)
  • Athena Elafrou (NVIDIA)
  • Chloe Alverti (National Technical University of Athens)
  • David Schall (Technical University of Munich)
  • Felix Eberhardt (IBM Germany Research & Development)
  • Haris Volos (University of Cyprus)
  • João Pedro Barreto (INESC-ID, Universidade de Lisboa)
  • Jonas Dann (ETH Zurich)
  • Konstantinos Kanellopoulos (ETH Zurich)
  • Kyle Hale (Oregon State University)
  • Manolis Katsaragakis (National Technical University of Athens)
  • Michal Friedman (ETH Zurich)
  • Sergey Blagodurov (AMD Research)
  • Vassilis Vassiliadis (IBM Research Europe)
  • Wenqi Jiang (ETH Zurich)

Past Editions

Contacts

Email Us: hcdsworkshop[at]gmail[dot]com for any question.