Workshop Overview
Abstract
The future of computing systems is inevitably embracing a disaggregated and
composable pattern: from clusters of computers to pools of resources that can be dynamically combined
together and tailored around application requirements.
With new interconnects for interfacing CPU, memory and peripherals becoming a commodity (e.g., CXL),
disaggregation and composability in computer systems is expected to become a predominant design pattern.
This paradigm change increases the level of heterogeneity from what is possible with statically defined
servers to software-defined dynamically composed servers, resulting in an increased memory and
accelerators capacity/availability and improved resource utilization in a cost-effective way, reducing the
overall total cost of ownership.
This new class of systems, that we term Heterogeneous and Composable Disaggregated Systems (HCDS),
provide a system design approach for reducing the imbalance between workloads resource requirements and
the static availability of resources in a computing system, while making room for novel distributed system
approaches in processes communication and data exchange.
The HCDS workshop aims at exploring the novel research ideas around composable disaggregated systems and
their integration with operating systems and software runtimes to maximize the benefit perceived from user
workloads.
Important Dates
These dates are tentative and may still change.
- Paper submission deadline:
January 20 2025 (AoE)February 7 2025 (AoE) - Extended - Author notification:
February 10 2025 (AoE)February 24 2025 (AoE) - Extended - Camera ready submissions:
February 15 2025 (AoE)March 3 2025 (AoE) - Extended - Workshop: March 30 2025
Call for Papers
The HCDS workshop aims at exploring the novel research ideas around composable disaggregated systems and their integration with operating systems and software runtimes to maximize the benefit perceived from user workloads.
Papers are solicited from the areas, including, but not limited to:
Hardware and Prototyping
- Novel composable systems architectures (e.g., CXL based)
- Composable system prototypes and proof-of-concept
- Interconnect technologies (such as CXL)
- Memory pooling, and memory disaggregation
Modeling and Evaluation
- Heterogeneous Composable Systems simulation
- Characterization of heterogeneous composable systems from the perspective of performance, energy consumption and reliability
- New algorithms and performance models to manage and use HCDS
- Memory pooling, and memory disaggregation
System software and programming models/tools
- Operating system designs to support HCDS, such as memory profiling methods, memory management (e,g, page migration and allocation)
- Control plane software and runtime systems for management of composable systems
- Programming models for heterogeneous composable memory
- Analysis / profiling tools and techniques for composable systems
- Virtualization for composable heterogeneous systems
Applications and Use cases
- Use cases for heterogeneous composable systems, such as (but not limited to) deep-learning inference/training and scientific applications
Submission Instructions
Each manuscript will be evaluated with a double-blind review
process. Authors must omit at submission time their names or any information that can disclose
their identity. Manuscripts length must be 4-6 pages including figures and
tables but excluding references. All manuscripts must use the sigplan ACM conference style. It is also
expected that all accepted papers will be presented at the workshop by one of the authors.
Papers accepted to the workshop will have the chance to be published on the ACM Digital Library
following the new ACM open access publishing model.
We offer the possibility to opt-out from
publishing submitted work to the ACM proceedings. This applies for instance to authors wishing to
re-submit an extended version to another venue that does not allow the work to have appeared in
official proceedings or, the authors are not part of the ACM open network and do not have the funds for
supporting the proceedings processing costs.
In such case, if your manuscript is accepted, it will only be published on the workshop website.
If you are wishing to do so, send the organizers an email right after
submitting your manuscript.
Important note to authors about the new ACM open access publishing model
ACM has introduced a new open access publishing model for the International Conference Proceedings
Series (ICPS).
Authors based at institutions that are not yet part of the ACM Open program and do not qualify for
a
waiver will be required to pay an article processing charge (APC) to publish their ICPS article in
the ACM Digital Library. To determine whether or not an APC will be applicable to your article,
please follow the detailed guidance here.
Further information may be found on the ACM website, as follows:
- details of the new ICPS publishing model
- details of the ACM Open program
Submission Link
Workshop Program
| 09:00 – 09:05 | Opening Remarks |
| 09:05 – 09:50 |
Keynote: Hardware Constraints for Low-cost CXL Memory
Pools Daniel S. Berger (Microsoft Azure and University of Washington) Abstract: CXL promises to enable the vision of composable and disaggregated racks. While the CLX standard enables many inviting configurations, systems research should incorporate practical hardware constraints. Our work in Azure Research has contributed to the standardization, development, and deployment of CXL over the past five years. In this talk, we share lessons learned and our best knowledge of cost, performance, and deployment constraints from the perspective of a major cloud platform. We review deployment steps such as CXL 1.1 local memory expansion, CXL 2.0/3.0 memory pools, and CXL 3.0/3.1+ memory sharing. We also describe a novel CXL pool design point specifically targeted at scalable low-cost deployments. We discuss tradeoffs and implications for software stacks. |
| 09:50 – 10:05 |
Honey, I Shrunk the Guests -- Page Access Tracking using a Minimal
Virtualisation Layer
Presentation Dustin Nguyen (Friedrich-Alexander-Universität Erlangen-Nürnberg), Sebastian Rußer (Friedrich-Alexander-Universität Erlangen-Nürnberg), Maximilian Ott (Friedrich-Alexander-Universität Erlangen-Nürnberg), Rüdiger Kapitza (Friedrich-Alexander-Universität Erlangen-Nürnberg), Wolfgang Schröder-Preikschat (Friedrich-Alexander-Universität Erlangen-Nürnberg), Jörg Nolte (Brandenburgische Technische Universität Cottbus-Senftenberg) |
| 10:05 – 10:20 |
Pick Your Poison: Lightweight CXL Memory Tiering with ATLAS
Presentation João Póvoas (INESC-ID, Universidade de Lisboa), João Barreto (INESC-ID, Universidade de Lisboa) |
| 10:20 – 10:35 |
Towards Memory Disaggregation via NVLink C2C: Benchmarking
CPU-Requested GPU Memory Access
Presentation Felix Werner (HPI, University of Potsdam), Marcel Weisgut (HPI, University of Potsdam), Tilmann Rabl (HPI, University of Potsdam) |
| 10:30 – 11:00 | Break |
| 11:00 – 11:15 |
Towards Elastic Memory Allocation of Serverless Functions in Memory
Disaggregated Systems
Presentation Achilleas Tzenetopoulos (National Technical University of Athens), Dimosthenis Masouros (National Technical University of Athens), Dimitrios Soudris (National Technical University of Athens), Sotirios Xydis (National Technical University of Athens) |
| 11:15 – 11:30 |
Storage cluster for persistency, CXL pools for caching
Presentation Karim Manaouil (The University of Edinburgh), Antonio Barbalace (The University of Edinburgh), Shai Aviram Bergman (Huawei Zurich Research Center), Zhou Xing Wang (Huawei), Yang Zhe (Huawei), Ji Zhang (Huawei) |
| 11:30 – 11:45 |
Move your code, not your data
Presentation Michael Giardino (Huawei), Siddharth Gupta (Huawei), Lukas Humbel (Huawei), Rene Mueller (Huawei), Anirban Nag (Huawei) |
| 11:45 – 12:00 |
Enabling Cloud-Scale Distributed Capabilities
Presentation Otto White (Imperial College London), Yaoxin Jing (Imperial College London), Adrien Ghosn (Microsoft Azure Research), Michael Steiner (Intel Labs), Anjo Vahldiek-Oberwagner (Intel Labs), Mona Vij (Intel Labs), Lluis Vilanova (Imperial College London) |
| 12:00 – 12:15 |
Cross-Vendor GPU Programming: Extending CUDA Beyond NVIDIA
Presentation Manos Pavlidakis (Spectral Compute), Chris Kitching (Spectral Compute), Nicholas Tomlinson (Spectral Compute), Michael Søndergaard (Spectral Compute) |
| 12:15 – 12:35 | Lightning talks (5 mins per talk)
Rethinking Applications' Address Space with CXL shared memory pools Presentation Tong Xing (The university of Edinburgh), Antonio Barbalace (The university of Edinburgh) Where are the Joules? Energy Demand Analysis of Heterogeneous Memory Technologies Presentation Thomas Preisner (Friedrich-Alexander-Universität Erlangen-Nürnberg), Dustin Tien Nguyen (Friedrich-Alexander-Universität Erlangen-Nürnberg), Manuel Vögele (Ruhr-Universität Bochum), Matthias Szymanski (Ruhr-Universität Bochum), Timo Hönig (Ruhr-Universität Bochum), Rüdiger Kapitza (Friedrich-Alexander-Universität Erlangen-Nürnberg), Wolfgang Schröder-Preikschat (Friedrich-Alexander-Universität Erlangen-Nürnberg) wBPF: A tracer for CXL pooling systems Presentation Yusheng Zheng (UC Santa Cruz), Tong Yu (Eunomia Inc), Yiwei Yang (UC Santa Cruz), Andrew Quinn (UC Santa Cruz) eGPU: Extending eBPF Programmability and Observability to GPUs Presentation Yiwei Yang (UC Santa Cruz), Tong Yu (Eunomia Inc), Yusheng Zheng (UC Santa Cruz), Andrew Quinn (UC Santa Cruz) |
Committees
Organizing Committee
- Christian Pinto (IBM Research Europe, Ireland)
- Dong Li (UC Merced, CA, USA)
- Thaleia Dimitra Doudali (IMDEA Software Institute, Spain)
- Christina Giannoula (University of Toronto, Canada)
- Jie Ren (William & Mary, VA, USA)
Program Committee
- Antonio J. Peña (Barcelona Supercomputing Center)
- Archit Patke (UIUC)
- Chloe Alverti (UIUC)
- Constantinos Evangelinos (IBM Research)
- Dimosthenis Masouros (NTUA)
- Felix Eberhardt (IBM)
- Haris Volos (University of Cyprus)
- Hasan Al Maruf (AMD)
- João Pedro Barreto (INESC-ID, Universidade de Lisboa)
- Kyle Hale (Oregon State)
- Michael Giardino (Huawei)
- Michael Aguilar (Sandia National Labs)
- Phil Cayton (Intel)
- Sergey Blagodurov (AMD Research)
- Vassilis Vassiliadis (IBM Research Europe)
- Alexandros Daglis (Georgia Tech)
- Tilmann Rabl (HPI, University of Potsdam)
- Andreas Grapentin (IBM)
Past Editions
Contacts
Email Us: hcdsworkshop[at]gmail[dot]com for any question.